This invention generally relates to a digital filter, and more particularly to a digital filter which sequentially delays a binary coded input for producing an output accruing from weighting and adding of the input delayed.
In a digital filter, an output at a given time is determined according to a past output and a weighted sum of the past and present inputs. In principle, such a digital filter comprises a plurality of multipliers for applying a plurality of weights to the input signal, a delay circuit for delaying the outputs of respective multipliers, and an adder which adds together the output of a multiplier of a succeeding stage and the output of a multiplier of a preceding stage. However, in a digital filter of high order, it is necessary to provide a multiplier, a delay circuit and an adder for each weighting stage, thus requiring a large number of such circuit elements. Particularly, provision of a plurality of stages of such complicated circuits as the multipliers increases the number of the arithmetic operations, thus increasing the size of the filter.
One approach to the solution to this problem is disclosed in U.S. Pat. No. 3,777,130 to Croisier et al entitled "Digital Filter for PCM Encoded Signals". The invention of this application also contemplates an approach to a similar problem and improves Croisier et al in that the memory capacity is reduced and the application to adaptive filters is facilitated.